Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAM”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.” A controller instantiated in programmably configurable circuitry of an FPGA (“FPGA fabric”), including one or more BRAMs, which communicated with an embedded microprocessor operated at about half the operating frequency of the embedded microprocessor (“processor”) due to the operating speed of the BRAM or BRAMs employed. Though control input to a processor may indicate a ratio of these two clock frequencies, providing different clock signals to BRAM and a processor introduces other timing issues. Other limitations of prior controllers employed in an FPGA include inability to use processor internal cache, lack of interrupts, and lack of access to processor internal timers.
Accordingly, it would be desirable and useful to provide a controller capable of operating at the frequency of operation of the processor. Furthermore, it would be desirable and useful to provide a controller capable of overcoming one or more of the other above-mentioned limitations.